Correlators are often used in many different types of processing systems, such as a tracking and location system, where time and angle of arrival have to be determined. Other information can be correlated, such as video and radar signals, as well as tracking and location information. In one proposed tracking and location system, a chirp waveform can be processed with an oscillator and associated circuits to increase the bandwidth. A correlator can be used as a matched filter for processing the chirp waveform, including the step of demodulating the chirp waveform.
One type of complex correlator has a basic function. It compares a reference to an incoming signal and gives a complex correlation. In emerging technologies, it is desirable to handle high data rates, such as four megabits a second. Correlators, however, become much more complicated when a quadrature input is required, e.g., an I and Q input, not just a real input. For example, a video correlator may have a channel data in and quantisizes a number of bits and correlates 1,000 samples of single points. It is necessary, however, when quadrature inputs are used to perform a cross correlation, which increases complexity. It is necessary to compare complex reference points to incoming data and determine a value, and then correlate more data again, such as 250 nanoseconds later.
Typically, larger correlators run slower. When correlators at a very low data rate, it is possible to take the data in and calculate thousands of point correlations. The time involved is extensive. These prior art types of correlators had difficulty reaching high rates, such as 4 Mbs. There was no optimal solution found between parallel and serial data flow, nor the loading of references.
Additionally, prior art correlators typically cannot be cascaded. Cascading correlator chips is relevant for complex correlators that have I and Q quadrature channels. Having these two channels will usually double the size of the gates and increase the complexity of multiplexers. As to the cascading of multiple correlator chips in the past, if a correlator had 1,000 samples and it was necessary to have 2,000 samples, a designer would take two 1,000 sample correlators, input the data, and then run through a delay with a shift register or RAM based delay and feed it to two chips. Additionally, reference data were not efficiently loaded, and storage of data and references using traditional shift register flip flops was not efficient.